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Differential difference amplifier FGMOS for electrocardiogram signal acquisition

Patricia Mejia-Chavez, Juan C. Sánchez, Jose Velazquez-Lopez

Open publisher page 3 citations

Abstract

In this paper a CMOS Instrumentation Amplifier (IA) for Electrocardiogram (ECG) acquisition systems is presented. This IA, configured as Differential Difference Amplifier (DDA), achieves high Common Mode Rejection Ratio (CMRR), high input impedance and low dc output voltage which are essential attributes for this building block. Besides, an innovative technique in CMOS analog design named Floating Gate (FG) is applied in the DDA designed to reduce offset. The presented IA is implemented in standard 0.5μm CMOS process working with α1.5V power supply. The dc offset voltage is reduced to 39μV, differential gain obtained is 39dB, CMRR reaches 136dB@10Hz and the input referred noise obtained is 3.7μV/√Hz.

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What this paper is about

In this paper a CMOS Instrumentation Amplifier (IA) for Electrocardiogram (ECG) acquisition systems is presented. This IA, configured as Differential Difference Amplifier (DDA), achieves high Common Mode Rejection Ratio (CMRR), high input impedance and low dc output voltage which are essential attributes for this building block. Besides, an innovative technique in CMOS analog design named Floating Gate (FG) is applied in the DDA designed to reduce offset. The presented IA is implemented in standard 0.5μm CMOS process working with α1.5V power supply. The dc offset voltage is reduced to 39μV, differential gain obtained is 39dB, CMRR reaches 136dB@10Hz and the input referred noise obtained is 3.7μV/√Hz.

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Available abstract

In this paper a CMOS Instrumentation Amplifier (IA) for Electrocardiogram (ECG) acquisition systems is presented. This IA, configured as Differential Difference Amplifier (DDA), achieves high Common Mode Rejection Ratio (CMRR), high input impedance and low dc output voltage which are essential attributes for this building block. Besides, an innovative technique in CMOS analog design named Floating Gate (FG) is applied in the DDA designed to reduce offset. The presented IA is implemented in standard 0.5μm CMOS process working with α1.5V power supply. The dc offset voltage is reduced to 39μV, differential gain obtained is 39dB, CMRR reaches 136dB@10Hz and the input referred noise obtained is 3.7μV/√Hz.

Key concepts: Instrumentation amplifier, Common-mode rejection ratio, Input offset voltage, CMOS, Differential amplifier, Electronic engineering, Electrical engineering, Amplifier

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