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2003•Unpublished venueRequires access

A 3.6 Gb/s 340 mW 16:1 pipe-lined multiplexer using SOI-CMOS technology

Toru Nakura, Keisuke Ueda, Kazuya Kubo, Warren Fernandez, Yoshio Matsuda, Kazuki Mashiko

Open publisher page 6 citations

Abstract

This paper describes a 16:1 multiplexer (MUX) using a 0.18 /spl mu/m partially-depleted SOI-CMOS technology. Owing to a selector type architecture with a pipeline structure as well as small junction capacitances of SOI-CMOS devices, the MUX achieves 3.6 Gbps operation dissipating 340 mW at a power supply of 2.0 V.

About this research paper

What this paper is about

This paper describes a 16:1 multiplexer (MUX) using a 0.18 /spl mu/m partially-depleted SOI-CMOS technology. Owing to a selector type architecture with a pipeline structure as well as small junction capacitances of SOI-CMOS devices, the MUX achieves 3.6 Gbps operation dissipating 340 mW at a power supply of 2.0 V.

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OpenAlex reports 6 citations for this work. Citation counts describe recorded attention and do not establish research quality.

Key contribution

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Method / approach

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Available abstract

This paper describes a 16:1 multiplexer (MUX) using a 0.18 /spl mu/m partially-depleted SOI-CMOS technology. Owing to a selector type architecture with a pipeline structure as well as small junction capacitances of SOI-CMOS devices, the MUX achieves 3.6 Gbps operation dissipating 340 mW at a power supply of 2.0 V.

Key concepts: Multiplexer, CMOS, Silicon on insulator, Pipeline (software), Electrical engineering, Multiplexing, Optoelectronics, Materials science

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