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2006•Unpublished venueRequires access

On the Number of 3-D IC Floorplan Configurations and a Solution Perturbation Method with Good Convergence

Song Chen, Takeshi Yoshimura

Open publisher page 2 citations

Abstract

3D IC can significantly alleviate the interconnect problem coming with the decreasing feature size and increasing integrated density. In this work, we concentrate on the 3D IC floorplanning. It is proved that the number of configuration of 3D floorplans is less than that of planar floorplans. Sequence pair is extended (P-SP) to represent 3D IC floorplans. A new solution perturbation method remove and insertion (RI) is implemented based on the technique of enumerating insertion points in P-SP, which is used in the traditional simulated annealing algorithm. The experimental results demonstrate the efficiency and the effectiveness of the proposed method

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What this paper is about

3D IC can significantly alleviate the interconnect problem coming with the decreasing feature size and increasing integrated density. In this work, we concentrate on the 3D IC floorplanning. It is proved that the number of configuration of 3D floorplans is less than that of planar floorplans. Sequence pair is extended (P-SP) to represent 3D IC floorplans. A new solution perturbation method remove and insertion (RI) is implemented based on the technique of enumerating insertion points in P-SP, which is used in the traditional simulated annealing algorithm. The experimental results demonstrate the efficiency and the effectiveness of the proposed method

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Available abstract

3D IC can significantly alleviate the interconnect problem coming with the decreasing feature size and increasing integrated density. In this work, we concentrate on the 3D IC floorplanning. It is proved that the number of configuration of 3D floorplans is less than that of planar floorplans. Sequence pair is extended (P-SP) to represent 3D IC floorplans. A new solution perturbation method remove and insertion (RI) is implemented based on the technique of enumerating insertion points in P-SP, which is used in the traditional simulated annealing algorithm. The experimental results demonstrate the efficiency and the effectiveness of the proposed method

Key concepts: Floorplan, Simulated annealing, Integrated circuit layout, Interconnection, Perturbation (astronomy), Planar, Annealing (glass), Computer science

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