HW/SW interface synthesis based on avalon bus specification for Nios-oriented SoC design

HW/SW interface synthesis plays an important role in systems-on-chip design. In this paper, we propose a new HW/SW interface synthesis design method aiming at the Nios-based SoC platform. Our main motivation is to separate the consideration of interface circuits from HW/SW modules design, leaving SW modules in the Nios processor and HW modules in the FPGA as peripherals. Different interface circuits will be kept as templates in interface library customized for different bus structures and transfer modes. When interface synthesizing, HW modules themselves are left with no changes; they only need to select different interface templates from the library according to the structure and transfer mode of the bus they connect to. The experimental results show this design methodology can efficiently solve the HW/SW interface synthesis problems on the Nios platform mentioned above well.