A DATACOMM LABORATORY WITH FPGAS IN A MICROPROCESSOR INTERFACING COURSE

Teaching undergraduate students about interfacing of microprocessors and microcontrollers in real-time systems is challenging because the circuits have moved from medium to increasingly higher frequencies (multimega- and giga hertz), while wired interfacing has been augmented with wireless interfacing. The trend to design reliable and small-footprint complex digital subsystems also calls for field programmable gate arras (FPGAs). This paper describes an attempt to accommodate the changes through a development of a new FPGA-based lab in an undergraduate course called Microprocessor Interfacing (μI) that has been offered at the University of Manitoba for many years now [1-4]. The course presents real-time wired and wireless interfacing of microcontrollers, microprocessors, and microcomputers to the external world, including interfacing of input/output (I/O) devices with minimum hardware and software, as well as data acquisition with and without microprocessors, data communications, transmission and logging with embedded computers. The following topics are covered: (i) introduction on computing, architectures, processors, and technologies, (ii) architecture and organization of small computer buses, and synchronization of data transfers on local buses (iii) digital input and output (I/O), (iv) digital-to-analog (D/A) and analog-to-digital (A/D) signal conversions and converters, (v) and interfacing aspects in data communications, including encoding, modulation, error detection and forward error protection. The course also includes (a) demonstrations of bus architectures, modules, systems, and new devices, as well as (b) updates on new concepts, technologies, protocols, and software. The laboratories are innovative in terms of three levels of complexity: the Tier1 level includes five 3-hour standard labs designed for all students, the Tier2 is designed for more experienced students, and the Tier3 level lab is designed as a project for groups of students with demonstrated prior design and implementation experience [3]. This paper describes a new laboratory in this course designed to show how to achieve asynchronous data communications using both VLSI components and field programmable gate arrays (FPGA). The first embodiment is designed to illustrate the principles of operation, while the second is to demonstrate how complex functional subsystems can be implemented in FPGA reconfigurable hardware. The laboratory has been used in the course, and produced encouraging results.