Nobuhiko Omori, Hans Jürgen Mattausch
Abstract
Fast and compact central arbiter circuits for detection and regulation of access conflicts in memories with multiple ports are proposed. A layout study in 0.5 µm, 2 metal CMOS technology verifies that area-overhead and access time penalty are small up to 32 ports.
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Fast and compact central arbiter circuits for detection and regulation of access conflicts in memories with multiple ports are proposed. A layout study in 0.5 µm, 2 metal CMOS technology verifies that area-overhead and access time penalty are small up to 32 ports.
Key concepts: Arbiter, CMOS, Computer science, Overhead (engineering), Access time, Electronic circuit, Embedded system, Computer hardware