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2013•Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIERequires access

Towards manufacturing a 10nm node device with complementary EUV lithography

Jan V. Hermans, Huixiong Dai, Ardavan Niroomand, David W. Laidler, Ming Mao, Yong Mei Chen, Philippe J. Leray, Chris S. Ngai, Shaunee Cheng

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Abstract

For device manufacturing at the 10nm node (N10) and below, EUV lithography is one of the technology options to achieve the required resolution. Besides high throughput and extreme resolution, excellent wafer CD, overlay and defect control are also required. In this paper, we discuss two wafer CD uniformity issues, the effect of the reticle black border and photon shot noise. The readiness of EUV lithography for N10 will be discussed by showing on-product imaging and overlay performance of a self aligned via layer inserted with EUV lithography. EUV single patterning results will be discussed by comparing the imaging performance of our NXE:3100 cluster to the NXE:3300 at ASML. Last but not least, the extendibility of EUV lithography towards sub 10nm patterning will be discussed by demonstrating sub 10nm half pitch LS patterns with EUV single Self Aligned Double Patterning (SADP).

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What this paper is about

For device manufacturing at the 10nm node (N10) and below, EUV lithography is one of the technology options to achieve the required resolution. Besides high throughput and extreme resolution, excellent wafer CD, overlay and defect control are also required. In this paper, we discuss two wafer CD uniformity issues, the effect of the reticle black border and photon shot noise. The readiness of EUV lithography for N10 will be discussed by showing on-product imaging and overlay performance of a self aligned via layer inserted with EUV lithography. EUV single patterning results will be discussed by comparing the imaging performance of our NXE:3100 cluster to the NXE:3300 at ASML. Last but not least, the extendibility of EUV lithography towards sub 10nm patterning will be discussed by demonstrating sub 10nm half pitch LS patterns with EUV single Self Aligned Double Patterning (SADP).

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Available abstract

For device manufacturing at the 10nm node (N10) and below, EUV lithography is one of the technology options to achieve the required resolution. Besides high throughput and extreme resolution, excellent wafer CD, overlay and defect control are also required. In this paper, we discuss two wafer CD uniformity issues, the effect of the reticle black border and photon shot noise. The readiness of EUV lithography for N10 will be discussed by showing on-product imaging and overlay performance of a self aligned via layer inserted with EUV lithography. EUV single patterning results will be discussed by comparing the imaging performance of our NXE:3100 cluster to the NXE:3300 at ASML. Last but not least, the extendibility of EUV lithography towards sub 10nm patterning will be discussed by demonstrating sub 10nm half pitch LS patterns with EUV single Self Aligned Double Patterning (SADP).

Key concepts: Extreme ultraviolet lithography, Multiple patterning, Reticle, Lithography, Extreme ultraviolet, Next-generation lithography, Wafer, Immersion lithography

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