2012Unpublished venueRequires access

TM-Dissector: An overhead model for software transactional memory

Xu Li, Kai Lü, Xu Zhou

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Abstract

Transactional memory has been proposed as an alternative to the traditional lock-based approach to express and manage concurrency in the multicore era. Among transactional memory techniques, software transactional memory (STM) is the most flexible and widely researched. However, researches show that STM suffers performance problem. In this pager, we present an overhead model for STM and our model could direct programmers to build more efficient program through STM.

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What this paper is about

Transactional memory has been proposed as an alternative to the traditional lock-based approach to express and manage concurrency in the multicore era. Among transactional memory techniques, software transactional memory (STM) is the most flexible and widely researched. However, researches show that STM suffers performance problem. In this pager, we present an overhead model for STM and our model could direct programmers to build more efficient program through STM.

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Available abstract

Transactional memory has been proposed as an alternative to the traditional lock-based approach to express and manage concurrency in the multicore era. Among transactional memory techniques, software transactional memory (STM) is the most flexible and widely researched. However, researches show that STM suffers performance problem. In this pager, we present an overhead model for STM and our model could direct programmers to build more efficient program through STM.

Key concepts: Software transactional memory, Transactional memory, Computer science, Lock (firearm), Concurrency, Transactional leadership, Multi-core processor, Pager

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