A mixed-signal simulator for VHDL-AMS

Capable and efficiency simulators are in demand for designing complex analog and mixed-signal circuits and systems. With the standardization of VHDL-AMS, the demand is being realized. VHDL-AMS is an Analog and Mixed-Signal Extensions to VHDL. This paper introduces a mixed-signal simulator for it. The simulator was developed on the original VHDL digital simulation environment. An analog kernel has been integrated into the environment for the simulation of the continuous behavior of a model. The paper presents the algorithms adopted in the analog kernel and the synchronization of the digital and analog executions. The performance of the simulator is examined by mixed-signal examples.