Low-Latency Turbo Decoder Design by Concurrent Decoding of Component Codes

Recently, there has been intensive focus on turbo codes which have low decoding latency. To reduce the iterative delay resulted from (de)interleaver; a new parallel algorithm for turbo decoder is proposed. Different than the previous approaches which use multiple units to process sub-block MAP decoding in parallel, the new parallel turbo decoder immediately passes the extrinsic information of one component decoder to the other decoders bit-by-bit. The decoding processes of component decoders perform concurrently and the (de)interleaver delay is eliminated. Simulation results demonstrate that with this parallel scheme, decoding latency is reduced while the performance in terms of BER is comparable, and in some cases superior, to a general turbo decoder. Furthermore, the proposed parallel algorithm can be used to cooperate with those parallel MAP decoding schemes to reduce more decoding latency.