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2010•AIP conference proceedingsRequires access

Optimization and Comparison of 4-Stage Inverter, 2-i∕p NAND Gate, 2-i∕p NOR Gate Driving Standard Load By Using Logical Effort

Satyajit Anand, P. K. Ghosh, Ravi B. Patel, Bharat Singh

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Abstract

Application of logical effort on transistor‐level analysis of 4‐stage inverter, 2‐i/p 4 stage NAND gate, and 2‐i/p 4 stage NOR gate is presented. Logical effort method is used to estimate delay and to evaluate the validity of the results obtained by using logical effort. The tested gate topologies were 4‐stage inverter, 2‐i/p‐4 stage NAND gate and, 2‐i/p 4 stage NOR gate. The quality of the obtained estimates is validated by circuit simulation using T‐SPICE for 1.8V, 180 nm technologies.

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What this paper is about

Application of logical effort on transistor‐level analysis of 4‐stage inverter, 2‐i/p 4 stage NAND gate, and 2‐i/p 4 stage NOR gate is presented. Logical effort method is used to estimate delay and to evaluate the validity of the results obtained by using logical effort. The tested gate topologies were 4‐stage inverter, 2‐i/p‐4 stage NAND gate and, 2‐i/p 4 stage NOR gate. The quality of the obtained estimates is validated by circuit simulation using T‐SPICE for 1.8V, 180 nm technologies.

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Available abstract

Application of logical effort on transistor‐level analysis of 4‐stage inverter, 2‐i/p 4 stage NAND gate, and 2‐i/p 4 stage NOR gate is presented. Logical effort method is used to estimate delay and to evaluate the validity of the results obtained by using logical effort. The tested gate topologies were 4‐stage inverter, 2‐i/p‐4 stage NAND gate and, 2‐i/p 4 stage NOR gate. The quality of the obtained estimates is validated by circuit simulation using T‐SPICE for 1.8V, 180 nm technologies.

Key concepts: NAND gate, Inverter, NOR gate, Spice, Gate equivalent, Logic gate, NAND logic, Transistor

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