Cascaded cross‐switched multilevel inverter in symmetric and asymmetric conditions

This study proposes and analyses a new cascaded multilevel inverter in both symmetric and asymmetric conditions. Firstly, the topology is presented in general form and then it is optimised. For any given number of voltage levels, the proposed topology reduces the number of switches. In the symmetric condition, the proposed topology offers capability of charge balance control method while reducing the number of switches. Also, unlike the other reduced switch topologies, the proposed topology does not increase the total standing voltage of the switches in comparison with the conventional cascaded H‐bridge (CHB) multilevel inverter. In the asymmetric condition, the proposed topology has highest output voltage resolution while keeping the total standing voltage equal to the CHB topology. In other words, in both symmetric and asymmetric conditions the number of switches in the proposed topology is lower than that of the CHB topology. However, both the proposed topology and also the CHB topology have the same total standing voltage on the switches. Other asymmetric topologies use higher number of switches and have higher total standing voltage in comparison with the proposed asymmetric topology. A modified phase‐shifted‐pulse width modulation is also presented for the proposed symmetric topology. The proposed topology is verified with simulation and experimental results.