Implementation of an optimizing compiler for VHDL

We present techniques used to implement an optimizing compiler for the VHSIC hardware description language (VHDL). We present details about the LR parser used to parse the input program. An efficient intermediate representation, called a process graph, is constructed as a result of the parsing. This representation is chosen to facilitate the ease of data flow analyses and optimizations. The process graph is a reducible flow graph because of the restricted subset of VHDL that we work with. The various data flow analyses and optimization techniques that have been implemented are described. This optimizing compiler is being used as a front end for a tool that performs behavioral synthesis.