Thermal stability of organic thin-film transistors with self-assembled monolayer dielectrics
Kenjiro Fukuda, Tomoyuki Yokota, Kazunori Kuribara, Tsuyoshi Sekitani, Ute Zschieschang, Hagen Klauk, Takao Someya
Abstract
Kenjiro Fukuda, Tomoyuki Yokota, Kazunori Kuribara, Tsuyoshi Sekitani, Ute Zschieschang, Hagen Klauk, Takao Someya
Abstract
We have investigated the annealing effects on 2 V-operation pentacene organic thin-film transistors (TFTs) with self-assembled monolayer-based gate dielectrics. When pentacene TFTs without passivation layers are annealed at 100 °C, the pentacene crystal structure changes to the bulk phase, resulting in an irreversible degradation of electronic performances. This degradation is suppressed by a 2.5-μm-thick passivation layer. The mobility of the encapsulated TFTs decreases by only 12% upon annealing at 140 °C. We have also investigated the bias-stress effect and found the drain current of low-voltage pentacene TFTs annealed at 70 °C decreases by 1% during continuous bias stress for 1 h.
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We have investigated the annealing effects on 2 V-operation pentacene organic thin-film transistors (TFTs) with self-assembled monolayer-based gate dielectrics. When pentacene TFTs without passivation layers are annealed at 100 °C, the pentacene crystal structure changes to the bulk phase, resulting in an irreversible degradation of electronic performances. This degradation is suppressed by a 2.5-μm-thick passivation layer. The mobility of the encapsulated TFTs decreases by only 12% upon annealing at 140 °C. We have also investigated the bias-stress effect and found the drain current of low-voltage pentacene TFTs annealed at 70 °C decreases by 1% during continuous bias stress for 1 h.
Key concepts: Pentacene, Thin-film transistor, Passivation, Materials science, Monolayer, Annealing (glass), Dielectric, Threshold voltage