Applying reconfigurable RET across process window to create more robust manufacturing designs

Optical proximity corrections (OPC) applied to design layouts are targeted for the nominal process condition FoEo that maintains manufacturing throughput and yield. For designs at 130 nm and above, this is usually sufficient to provide the needed resolution enhancement technology (RET) corrections for high-yield manufacturing. However, for sub-100 nm designs, lack of feature fidelity across the process window becomes a significant contributor to yield loss. It becomes critical to simulate across the lithography process window to predict feature behavior over a wide range of focus and exposure (FE) conditions. KLA-Tencor's DesignScan tool simulates the performance of a design across the process window and detects any defects which are then flagged for repair. In the conventional OPC flow, correction of defects entails changing the OPC recipe and redecorating the entire layout. Aprio's reconfigurable OPC technology allows one to compute more aggressive OPC corrections at the error locations. This reconfigured OPC replaces the original corrections only at the error locations. This allows prior OPC results to be re-used. The halo or boundary areas associated with the stitching of the modified OPC are simulated and verified and the results are converged back into the layout. This allows the designer to start with a nominal OPC design and by applying reconfigurable OPC technology, eliminate printability errors in the process window, expand the process window, resulting in more robust design performance across the process window. This mask design inspection and optimization method improves yield and shortens cycle time to first wafers, thus providing closure for the design to manufacturing loop.