1988•Electronics LettersRequires access

New hardware architecture for fast raster image generation

S.-S. Kim, K.S. Eo, Chong‐Min Kyung

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Abstract

We describe a new hardware architecture known as an edge painting tree (EPT) using pipelined binary trees for fast generation of scanline images for raster scan graphics. The hardware complexity of EPT is much smaller than that of earlier raster graphics engines owing to the use of 1 bit logic rather than log2P bit logic where P is the number of pixels per scanline.

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What this paper is about

We describe a new hardware architecture known as an edge painting tree (EPT) using pipelined binary trees for fast generation of scanline images for raster scan graphics. The hardware complexity of EPT is much smaller than that of earlier raster graphics engines owing to the use of 1 bit logic rather than log2P bit logic where P is the number of pixels per scanline.

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Available abstract

We describe a new hardware architecture known as an edge painting tree (EPT) using pipelined binary trees for fast generation of scanline images for raster scan graphics. The hardware complexity of EPT is much smaller than that of earlier raster graphics engines owing to the use of 1 bit logic rather than log2P bit logic where P is the number of pixels per scanline.

Key concepts: Raster graphics, Scan line, Raster scan, Computer science, Graphics, Computer graphics (images), Pixel, Architecture

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