Temporary bonding for Chips In Wafer processing
Jean-Charles Souriau, A. Jouve, N. Sillon
Abstract
Jean-Charles Souriau, A. Jouve, N. Sillon
Abstract
Chip In Wafer is a very challenging concept because this solution allows wafer scale processes for System in Package and a very high miniaturization and performance level. This paper describes a technologies developed for Chip integration In Wafer (CIW). The approach consists in reconstituting a wafer from heterogeneous chips embedded in a resin with the active sides coplanar. This paper present the development of a new process using wafer substrate including alignment marks and a transparence adhesive which allow an accurate dies positioning and holding during the polymer molding. The process presented in this paper is compatible for chips in polymer wafer, chips in silicon wafer, chips in glass wafer and some other frame.
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Chip In Wafer is a very challenging concept because this solution allows wafer scale processes for System in Package and a very high miniaturization and performance level. This paper describes a technologies developed for Chip integration In Wafer (CIW). The approach consists in reconstituting a wafer from heterogeneous chips embedded in a resin with the active sides coplanar. This paper present the development of a new process using wafer substrate including alignment marks and a transparence adhesive which allow an accurate dies positioning and holding during the polymer molding. The process presented in this paper is compatible for chips in polymer wafer, chips in silicon wafer, chips in glass wafer and some other frame.
Key concepts: Wafer, Die preparation, Wafer backgrinding, Wafer-scale integration, Miniaturization, Wafer testing, Materials science, Wafer-level packaging