Optimized OPC approach for process window improvement

Within the past several years, IC design and manufacture technology node transits rapidly from 0.13um to 65nm and 45nm. Whatever the technology node is, the same goal that both the designer and the manufacturer put most of their effort on is how to improve the chip yield as high as possible. A bunch of evidences have shown that the final yield is extremely related to the pattern transfer from design to wafer. But with the critical dimension shrinks, the largest challenge that the whole industry meets is how to keep high fidelity while transferring the patterns. Since the process window is now very limited even with the assistance of kinds of resolution enhancement technology, a tiny process deviation may cause large critical dimension variation, which will result in significant device character change. Micro-lithography combined with Optical proximity correct is supposed to be the most critical stage in pattern transfer stage. But conventional OPC always use nominal model, which will not take random process variation into account during applying OPC. This work will demonstrate our experiment in OPC with process window model, which is then proved to have obvious improvement in pattern fidelity.