Gerry Kane, Joe Heinrich
Abstract
1. RISC Architecture: An Overview. 2. MIPS Processor Architecture Overview. 3. CPU Instruction Set Summary. 4. Memory Management System. 5. Caches. 6. Exception Processing. 7. FPU Overview. 8. FPU Instruction Set Summary and Instruction Pipeline. 9. Floating Point Exceptions. Appendixes. Index.
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1. RISC Architecture: An Overview. 2. MIPS Processor Architecture Overview. 3. CPU Instruction Set Summary. 4. Memory Management System. 5. Caches. 6. Exception Processing. 7. FPU Overview. 8. FPU Instruction Set Summary and Instruction Pipeline. 9. Floating Point Exceptions. Appendixes. Index.
Key concepts: Reduced instruction set computing, Computer science, Instruction set, Architecture, Computer architecture, Pipeline (software), Set (abstract data type), Operating system