Implementation of Can Bus Based System -on-Chip on Altera FPGA

A field-programmable gate array (FPGA) is an integrated circuit designed to be configured by a customer or a designer after manufacturing. FPGAs are going to rule in the future because of their flexibility, decreasing prices and increasingly better power efficiency. Often a soft processor is added in the FPGA design to get microcontroller like function- ality along-with other concurrent processing. The Altera Stratix FPGA series is built to meet low-power, cost-sensitive design needs, enabling to get to market faster. Altera's The Nios II processor core is a soft-core central processing unit (CPU) that can be program onto an Altera field programmable gate array gives the ultimate flexibility to achieve the exact performance required for your embed- ded design. This project aims at implementing a CAN(Controller Area Network) Bus , NIOS soft processor core based System-on-Chip on Altera FPGA. The CAN bus module implemented inside the FPGA accepts commands from external world and passes them onto NIOS soft core in appropriate format, for it to act on the received commands. Project task includes, Porting of NIOS soft processor core onto Altera FPGA, Implementing CAN soft module inside FPGA and Programming of NIOS soft core to perform tasks based on commands received on CAN bus. Designed SOC will implement a processor task, Programmable PWM Module. This module gives out PWM waveform .The frequency and duty cycle of PWM signal would be varied based on the values received through CAN bus via Nios processor. Block coding technique in Altera QUARTUS 2 software tool is used for the complete development of System on Chip.