Fast Universal Decoder for Block Error Correcting Codes using Parallel Comparison
Christopher Fritz, Adly T. Fam
Abstract
Christopher Fritz, Adly T. Fam
Abstract
In this work, a fast decoder for Block Error Correcting Codes is introduced. It is based on comparing the received code word, with possible errors, to all codewords without errors in parallel. The Hamming distances between the received code word and all the correct code words are computed in parallel, and then each Hamming distance is compared to all the correctable values it can attain simultaneously. The code word with the smallest Hamming distance is chosen to be the correct code word. Any match for such a value blocks the output of all higher values. The result is a very fast circuit and method for decoding with propagation delay independent of the number of code words. Next to each code word, the data word that it encodes is stored and therefore either the corrected code word or the corresponding data word can be outputted. This parallel design allows for high throughput and short latency, rendering it particularly suited for applications such as error correcting RAM and communication channels. The decoder is programmable for any block error correcting code within its hardware capacity. Additionally, it works equally well for linear as well as nonlinear block error correcting codes and therefore represents a universal decoder.
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In this work, a fast decoder for Block Error Correcting Codes is introduced. It is based on comparing the received code word, with possible errors, to all codewords without errors in parallel. The Hamming distances between the received code word and all the correct code words are computed in parallel, and then each Hamming distance is compared to all the correctable values it can attain simultaneously. The code word with the smallest Hamming distance is chosen to be the correct code word. Any match for such a value blocks the output of all higher values. The result is a very fast circuit and method for decoding with propagation delay independent of the number of code words. Next to each code word, the data word that it encodes is stored and therefore either the corrected code word or the corresponding data word can be outputted. This parallel design allows for high throughput and short latency, rendering it particularly suited for applications such as error correcting RAM and communication channels. The decoder is programmable for any block error correcting code within its hardware capacity. Additionally, it works equally well for linear as well as nonlinear block error correcting codes and therefore represents a universal decoder.
Key concepts: Computer science, Hamming code, Code word, Constant-weight code, Error detection and correction, Word (group theory), Decoding methods, Block code