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2006•Unpublished venueRequires access

Package-on-Package (PoP) for Advanced PCB Manufacturing Process

Joseph Y. Lee, Jin-Yong Ahn, Jegwang Yoo, Joonsung Kim, Hwa‐Sun Park, Shuichi Okabe

Open publisher page 3 citations

Abstract

In the 1990's, both BGA (ball grid array) and CSP (chip size package) are entering their end in the front-end packaging materials and process technology. Both BGA and CSP like SMD (surface mount device) from the 1980's and THD (through-hole mount device) from the 1970's are reaching its own impasse in terms of maximizing its electrical, mechanical, and thermal performances, size, weight, and reliability. Now, 3D packages are the next phase for its future use in advanced PCB manufacturing process. They can be classified into wafer level, chip level, and package level stacking. So, package-on-package (PoP), a type of 3D package level stacking, is to be discussed in this paper (Kada et al.)

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What this paper is about

In the 1990's, both BGA (ball grid array) and CSP (chip size package) are entering their end in the front-end packaging materials and process technology. Both BGA and CSP like SMD (surface mount device) from the 1980's and THD (through-hole mount device) from the 1970's are reaching its own impasse in terms of maximizing its electrical, mechanical, and thermal performances, size, weight, and reliability. Now, 3D packages are the next phase for its future use in advanced PCB manufacturing process. They can be classified into wafer level, chip level, and package level stacking. So, package-on-package (PoP), a type of 3D package level stacking, is to be discussed in this paper (Kada et al.)

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Available abstract

In the 1990's, both BGA (ball grid array) and CSP (chip size package) are entering their end in the front-end packaging materials and process technology. Both BGA and CSP like SMD (surface mount device) from the 1980's and THD (through-hole mount device) from the 1970's are reaching its own impasse in terms of maximizing its electrical, mechanical, and thermal performances, size, weight, and reliability. Now, 3D packages are the next phase for its future use in advanced PCB manufacturing process. They can be classified into wafer level, chip level, and package level stacking. So, package-on-package (PoP), a type of 3D package level stacking, is to be discussed in this paper (Kada et al.)

Key concepts: Ball grid array, Quad Flat No-leads package, Package on package, Chip-scale package, Surface-mount technology, Stacking, Wafer-level packaging, Electronic packaging

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