A protocol for a new double-loop computer network and its implementation

In this paper a new double-loop computer network is presented, as well as its hardware implementation. The proposed protocol permits simultaneous transfer of variable-length messages even between interfering segments of the network. Various concurrent transmissions can also take place with this protocol. These operations, together with a completely distributed control mechanism, make this new network capable of providing automatic traffic regulation. In addition, the reliability of the system is improved. The nodes of the network can be implemented by existing programmable LSI communication protocol controllers. This simple hardware implementation and the above capabilities make the proposed network very attractive for local networks with high traffic demands. In this paper a node realization, based on the 8085A microprocessor chips, is also presented. Every node consists basically of two SDLC Chips, one DMA controller and the Interrupt Controller.