Leakage Power Reduction in Flip Flops by Using MTCMOS and ULP Switch

As feature size of the CMOS technology continues to scale down, leakage power has become an ever-increasing important part of the total power consumption of a chip. By analyzing the leakage path of flip flops, we propose a method to reduce the leakage power of flip flops in this paper. Experimental results show that the leakage power of the proposed flip flop can be reduced by an average of 72.35% and 21.88% in standby mode and in active mode respectively while the delay time stays the same and the expense of area is small.