A micro-power 4.8 ppm/°C CMOS voltage reference circuit for linear drop out regulator used in RFID
Shailesh Singh Chouhan, Kari A. I. Halonen
Abstract
Shailesh Singh Chouhan, Kari A. I. Halonen
Abstract
Low Drop Out (LDO) Regulator is used to maintain steady voltage in power generation blocks. Voltage reference is the most important component in LDO design. The output voltage of LDO is a multiple of the reference voltage. Band gap voltage reference circuits (BVRC) are utilized in LDO for this purpose. The output voltage of a bandgap reference circuit is based on the bandgap voltage of the semiconductor: a well-defined, temperature independent physical value. Diodes and Bipolar Junction Transistors (BJTs) are used for implementing BVRC. In sub-micron CMOS digital processes, lack of lateral pnps can be seen as a disadvantage. In this work, we are proposing a completely MOS based voltage reference scheme. The proposed voltage reference has been implemented using standard 0.18 μm CMOS technology. It generates a constant reference voltage of 594.72mV. The operating supply voltage for the proposed circuit ranges from 1.25V to 2V. The layout area is 0.0055 mm2, with maximum power dissipation of 2.5 μW, simulated at 2V supply voltage. The operating temperature ranges from -10 °C to 110 °C with a temperature coefficient of 4.8 ppm/°C. The simulated line sensitivity is 0.2mV/V, with the supply voltage variation from 1.25V to 2V and the PSRR at 100Hz is -67dB.
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Low Drop Out (LDO) Regulator is used to maintain steady voltage in power generation blocks. Voltage reference is the most important component in LDO design. The output voltage of LDO is a multiple of the reference voltage. Band gap voltage reference circuits (BVRC) are utilized in LDO for this purpose. The output voltage of a bandgap reference circuit is based on the bandgap voltage of the semiconductor: a well-defined, temperature independent physical value. Diodes and Bipolar Junction Transistors (BJTs) are used for implementing BVRC. In sub-micron CMOS digital processes, lack of lateral pnps can be seen as a disadvantage. In this work, we are proposing a completely MOS based voltage reference scheme. The proposed voltage reference has been implemented using standard 0.18 μm CMOS technology. It generates a constant reference voltage of 594.72mV. The operating supply voltage for the proposed circuit ranges from 1.25V to 2V. The layout area is 0.0055 mm2, with maximum power dissipation of 2.5 μW, simulated at 2V supply voltage. The operating temperature ranges from -10 °C to 110 °C with a temperature coefficient of 4.8 ppm/°C. The simulated line sensitivity is 0.2mV/V, with the supply voltage variation from 1.25V to 2V and the PSRR at 100Hz is -67dB.
Key concepts: Bandgap voltage reference, Voltage reference, Power supply rejection ratio, Dropout voltage, Voltage regulator, Low-dropout regulator, CMOS, Electrical engineering