2012IEICE Electronics ExpressOpen access

Modified Booth encoding modulo (2n-1) multipliers

Lei Li, Jianhao Hu, Yiou Chen

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Abstract

(2n-1) is one of the most commonly used moduli in Residue Number Systems. In this express, we propose a novel Booth encoding architecture. Based on the proposed Booth encoding architecture, we can design high speed and high-efficient modulo (2n-1) multipliers, which are the fastest among all known modulo (2n-1) multipliers. The performance and the efficiency of the proposed multipliers are evaluated and compared with the earlier fastest modulo (2n-1) multipliers, based on a simple gate-count and gate-delay model. These results reveal that the proposed multipliers lead to average approximately 14% faster than the fastest known modulo (2n-1) multipliers.

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What this paper is about

(2n-1) is one of the most commonly used moduli in Residue Number Systems. In this express, we propose a novel Booth encoding architecture. Based on the proposed Booth encoding architecture, we can design high speed and high-efficient modulo (2n-1) multipliers, which are the fastest among all known modulo (2n-1) multipliers. The performance and the efficiency of the proposed multipliers are evaluated and compared with the earlier fastest modulo (2n-1) multipliers, based on a simple gate-count and gate-delay model. These results reveal that the proposed multipliers lead to average approximately 14% faster than the fastest known modulo (2n-1) multipliers.

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Available abstract

(2n-1) is one of the most commonly used moduli in Residue Number Systems. In this express, we propose a novel Booth encoding architecture. Based on the proposed Booth encoding architecture, we can design high speed and high-efficient modulo (2n-1) multipliers, which are the fastest among all known modulo (2n-1) multipliers. The performance and the efficiency of the proposed multipliers are evaluated and compared with the earlier fastest modulo (2n-1) multipliers, based on a simple gate-count and gate-delay model. These results reveal that the proposed multipliers lead to average approximately 14% faster than the fastest known modulo (2n-1) multipliers.

Key concepts: Modulo, Modulo operation, Arithmetic, Encoding (memory), Residue number system, Mathematics, Adder, Parallel computing

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