2008Unpublished venueRequires access

Evidence for threshold switching in the set process of NiO-based RRAM and physical modeling for set, reset, retention and disturb prediction

C. Cagli, Daniele Ielmini, Federico Nardi, Andrea Leonardo Lacaita

Open publisher page 54 citations

Abstract

This work addresses the set and reset mechanisms in NiO-based resistive-switching memory (RRAM) devices, presenting a new physics-based model for RRAM reliability and programming. We show experimental evidence that the set process is initiated by threshold switching, that is a reversible electronic transition to a high conductance state. We develop set/reset models for prediction of programming voltage and time under sweep or pulsed conditions. The speed limitations of RRAMs are then assessed by a detailed study of reset operation in the pulsed regime, showing evidence for over-reset under high-voltage, fast programming conditions (< 1 mus).

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What this paper is about

This work addresses the set and reset mechanisms in NiO-based resistive-switching memory (RRAM) devices, presenting a new physics-based model for RRAM reliability and programming. We show experimental evidence that the set process is initiated by threshold switching, that is a reversible electronic transition to a high conductance state. We develop set/reset models for prediction of programming voltage and time under sweep or pulsed conditions. The speed limitations of RRAMs are then assessed by a detailed study of reset operation in the pulsed regime, showing evidence for over-reset under high-voltage, fast programming conditions (< 1 mus).

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OpenAlex reports 54 citations for this work. Citation counts describe recorded attention and do not establish research quality.

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Available abstract

This work addresses the set and reset mechanisms in NiO-based resistive-switching memory (RRAM) devices, presenting a new physics-based model for RRAM reliability and programming. We show experimental evidence that the set process is initiated by threshold switching, that is a reversible electronic transition to a high conductance state. We develop set/reset models for prediction of programming voltage and time under sweep or pulsed conditions. The speed limitations of RRAMs are then assessed by a detailed study of reset operation in the pulsed regime, showing evidence for over-reset under high-voltage, fast programming conditions (< 1 mus).

Key concepts: Reset (finance), Resistive random-access memory, Set (abstract data type), Non-blocking I/O, Reliability (semiconductor), Process (computing), Computer science, Voltage

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