Design and implementation of a 1024-point high-speed FFT processor based on the FPGA

To design a Fast Fourier Transform (FFT) processor to meet the needs for high-speed and real-time signal processing. A 1024-point, 32-bit, fixed, complex FFT processor is designed based on a field programmable gate array (FPGA) by using the radix-2 decimation in frequency (DIF) algorithm and the pipeline structure in the butterfly module and the ping-pone operation in data storage unit. When the primary clock is 100 MHz, the 1024-point FFT calculation takes about 62.95 us. The processor is fast enough for processing the high-speed and real time signals. The result provides reference values that theoretical study of the FFT algorithm can be applied into the adaptive dynamic filter of an ultrasonic diagnostic system and an ultrasonic Doppler flow measurement system.