A 12-bit 320-MSample/s current-steering CMOS D/A converter in 0.44 mm/sup 2/

A 12-bit 320-MSample/s current-steering D/A converter in 0.18-/spl mu/m CMOS is presented. In order to achieve high linearity and spurious free dynamic range (SFDR), a large degree of segmentation has been used, with the seven most significant bits (MSBs) being implemented as equally weighted current sources. A "design-for-layout" approach has allowed this to be done in an area of just 0.44 mm/sup 2/. The increased switching noise associated with a high degree of segmentation has been reduced by a new latch architecture. Differential nonlinearity of /spl plusmn/0.3 LSB and integral nonlinearity of /spl plusmn/0.4 LSB have been measured. Low-frequency SFDR of 95 dB has been achieved, while SFDR at 320 MS/s remains above 70 and 60 dB for input frequencies up to 10 and 60 MHz, respectively. The converter consumes a total of 82 mW from 1.8-V and 3.3-V supplies. The validity of the techniques used has been demonstrated by fabricating the converter in two separate 0.18-/spl mu/m processes with similar results measured for both.