2009Journal of SemiconductorsOpen access

A 3.96 GHz phase-locked loop for mode-1 MB-OFDM UWB hopping carrier generation

Yongzheng Zheng, Weinan Li, Xia Lingli, Huang Yumei, Hong Zhiliang

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Abstract

A fully integrated phase-locked loop (PLL) is presented for a single quadrature output frequency of 3.96 GHz. The proposed PLL can be applied to mode-1 MB-OFDM UWB hopping carrier generation. An adaptive frequency calibration loop is incorporated into the PLL. The capacitance area in the loop filter is largely reduced through a capacitor multiplier. Implemented in a CMOS process, this PLL draws 13.0 mA current from a single 1.2 V supply while occupying 0.55 mm 2 die area. Measurement results show that the PLL achieves a phase noise of–70 dBc/Hz at 10 kHz offset and −113 dBc/Hz at 1 MHz offset. The integrated RMS jitter from 1 kHz to 10 MHz is 2.2 ps. The reference spur level is less than −68 dBc.

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A fully integrated phase-locked loop (PLL) is presented for a single quadrature output frequency of 3.96 GHz. The proposed PLL can be applied to mode-1 MB-OFDM UWB hopping carrier generation. An adaptive frequency calibration loop is incorporated into the PLL. The capacitance area in the loop filter is largely reduced through a capacitor multiplier. Implemented in a CMOS process, this PLL draws 13.0 mA current from a single 1.2 V supply while occupying 0.55 mm 2 die area. Measurement results show that the PLL achieves a phase noise of–70 dBc/Hz at 10 kHz offset and −113 dBc/Hz at 1 MHz offset. The integrated RMS jitter from 1 kHz to 10 MHz is 2.2 ps. The reference spur level is less than −68 dBc.

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Available abstract

A fully integrated phase-locked loop (PLL) is presented for a single quadrature output frequency of 3.96 GHz. The proposed PLL can be applied to mode-1 MB-OFDM UWB hopping carrier generation. An adaptive frequency calibration loop is incorporated into the PLL. The capacitance area in the loop filter is largely reduced through a capacitor multiplier. Implemented in a CMOS process, this PLL draws 13.0 mA current from a single 1.2 V supply while occupying 0.55 mm 2 die area. Measurement results show that the PLL achieves a phase noise of–70 dBc/Hz at 10 kHz offset and −113 dBc/Hz at 1 MHz offset. The integrated RMS jitter from 1 kHz to 10 MHz is 2.2 ps. The reference spur level is less than −68 dBc.

Key concepts: Phase-locked loop, dBc, Phase noise, Jitter, CMOS, PLL multibit, Electronic engineering, Offset (computer science)

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