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Some Studies on the Problem of Three-level NAND Network Synthesis

Avik Kumar Choudhury, K. Chakrabarti, DEBABRATA SARMA

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Abstract

The present paper is concerned with the problem of three-level economic NAND synthesis of general Boolean functions. It is shown that a. given Boolean function is first decomposed into a set of sub-functions, called φ functions. From a study of the properties of φ functions a method is finally suggested for three-level synthesis of Boolean functions with a fewer number of NAND gates. A method of finding the minimal three-level NAND solution for a given irredundant prime implicant cover of any Boolean function is also suggested.

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What this paper is about

The present paper is concerned with the problem of three-level economic NAND synthesis of general Boolean functions. It is shown that a. given Boolean function is first decomposed into a set of sub-functions, called φ functions. From a study of the properties of φ functions a method is finally suggested for three-level synthesis of Boolean functions with a fewer number of NAND gates. A method of finding the minimal three-level NAND solution for a given irredundant prime implicant cover of any Boolean function is also suggested.

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Available abstract

The present paper is concerned with the problem of three-level economic NAND synthesis of general Boolean functions. It is shown that a. given Boolean function is first decomposed into a set of sub-functions, called φ functions. From a study of the properties of φ functions a method is finally suggested for three-level synthesis of Boolean functions with a fewer number of NAND gates. A method of finding the minimal three-level NAND solution for a given irredundant prime implicant cover of any Boolean function is also suggested.

Key concepts: NAND gate, Computer science, Mathematics, Mathematical optimization, Algorithm, Logic gate

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