Parameters Improvement for Differential SRAM Using 180 nm Technology

This paper represents a technique for a designing differential 6T SRAM with improved parameters. In SRAM designing lowering power consumption and increasing noise margin have become two essential topics in every state of art. Static RAM (SRAM) is a form of memory that holds data in the form of static. Refreshing is not requiring in the SRAM circuit. Reduction of operating voltage in SRAM degrades the stability of the cell. Our 6T SRAM is proposed design in which we have calculated Read Margin (RM), Write Margin (WM), Power consumption with temperature or without temperature. It also consumes less power when compared to the 8T SRAM design. It provides the improved write margin, read margin when compared to the other SRAM designing. The simulation has been carried out on 180 nm CMOS technology. Tanner EDA tool is used for simulation.