2010•Analog Integrated Circuits and Signal ProcessingOpen access

2.5 Gb/s CMOS preamplifier for low-cost fiber-optic receivers

José Pozo, Wouter A. Serdijn, Aranzazu Otin, Santiago Celma

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Abstract

This paper reports an optical preamplifier intended for low-cost fiber-optic receivers. The preamplifier is based on a resistive shunt-feedback topology, is power-optimized and employs two different frequency compensation techniques, phantom zeros and shunt-peaking. The circuit is designed in a 1.8 V 0.18 μm CMOS technology. Experimental results report a transresistance of 58 dBΩ and a bandwidth of 1.5 GHz, respectively. Eye diagrams obtained at 2.5 Gb/s show a total jitter of 18 ps and a bit error rate (BER) of 10 −12 when the input current amplitude (I in ) is equal to or higher than 8.5 μA. Higher bit rates up to 3 Gb/s also have been tested achieving a BER of 10 −12 when I in ≥9.5 μA. The power consumption and die active area are 23.7 mW and 0.017 mm 2 , respectively.

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This paper reports an optical preamplifier intended for low-cost fiber-optic receivers. The preamplifier is based on a resistive shunt-feedback topology, is power-optimized and employs two different frequency compensation techniques, phantom zeros and shunt-peaking. The circuit is designed in a 1.8 V 0.18 μm CMOS technology. Experimental results report a transresistance of 58 dBΩ and a bandwidth of 1.5 GHz, respectively. Eye diagrams obtained at 2.5 Gb/s show a total jitter of 18 ps and a bit error rate (BER) of 10 −12 when the input current amplitude (I in ) is equal to or higher than 8.5 μA. Higher bit rates up to 3 Gb/s also have been tested achieving a BER of 10 −12 when I in ≥9.5 μA. The power consumption and die active area are 23.7 mW and 0.017 mm 2 , respectively.

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Available abstract

This paper reports an optical preamplifier intended for low-cost fiber-optic receivers. The preamplifier is based on a resistive shunt-feedback topology, is power-optimized and employs two different frequency compensation techniques, phantom zeros and shunt-peaking. The circuit is designed in a 1.8 V 0.18 μm CMOS technology. Experimental results report a transresistance of 58 dBΩ and a bandwidth of 1.5 GHz, respectively. Eye diagrams obtained at 2.5 Gb/s show a total jitter of 18 ps and a bit error rate (BER) of 10 −12 when the input current amplitude (I in ) is equal to or higher than 8.5 μA. Higher bit rates up to 3 Gb/s also have been tested achieving a BER of 10 −12 when I in ≥9.5 μA. The power consumption and die active area are 23.7 mW and 0.017 mm 2 , respectively.

Key concepts: Preamplifier, CMOS, Jitter, Electrical engineering, Physics, Power consumption, 4-bit, Bandwidth (computing)

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