The Viterbi Decoding Scheme for FPGA
Ke Han, Zhong Liang Deng, Lian Ming Xu
Abstract
Ke Han, Zhong Liang Deng, Lian Ming Xu
Abstract
This paper analyzes the principle of Viterbi algorithm which can be used in the norm of the mobile communication system. Then a new Viterbi decoding scheme of (2, 1, 7) convolutional code is presented for FPGA implementation. To take advantage of the FPGA, a new branch weight algorithm and uniform state weight memories is used. At last, a new decoding circuit which can work on 35MHz and can achieve 120 kbs in decoding speed was designed. To use the design of survival path exchange register module, it can decrease the power consumption and the RAM size.
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This paper analyzes the principle of Viterbi algorithm which can be used in the norm of the mobile communication system. Then a new Viterbi decoding scheme of (2, 1, 7) convolutional code is presented for FPGA implementation. To take advantage of the FPGA, a new branch weight algorithm and uniform state weight memories is used. At last, a new decoding circuit which can work on 35MHz and can achieve 120 kbs in decoding speed was designed. To use the design of survival path exchange register module, it can decrease the power consumption and the RAM size.
Key concepts: Viterbi decoder, Decoding methods, Computer science, Iterative Viterbi decoding, Convolutional code, Viterbi algorithm, Field-programmable gate array, Soft output Viterbi algorithm