Improved extraction of carrier concentration and depletion width from capacitance–voltage characteristics of silicon n+–p-well junction diodes

An accurate method is proposed for the extraction of the carrier concentration profile (pp well) and the depletion width (Wp well) in a p-well region from high-frequency capacitance measurements by accounting for the series resistance and the capacitance of the n+ region. Wp well was calculated from the capacitance in the p-well region (Cp well), while pp well was derived from the slope of the plot 1/Cp well2 versus reverse bias. The pp well extracted was compared with profiles obtained from spreading resistance probe results. The differences between the two techniques are within 15% in the accessible depletion width, which will be discussed in view of the depth resolution anticipated.