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1986•IEEE Journal of Solid-State CircuitsRequires access

An 8-bit 250 megasample per second analog-to-digital converter: operation without a sample and hold

B. Peetz, B.D. Hamilton, Jin-Yoeng Kang

Open publisher page 52 citations

Abstract

A monolithic, 8-bit, 250 megasample per second analog-to-digital converter (ADC) fabricated in an oxide-isolated bipolar process is described. The use of a flash ADC architecture at high speeds without a sample and hold leads to a number of error sources. The design of the converter is optimized to minimize the effects of these error sources. Experimental results are presented and compared with theory.

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What this paper is about

A monolithic, 8-bit, 250 megasample per second analog-to-digital converter (ADC) fabricated in an oxide-isolated bipolar process is described. The use of a flash ADC architecture at high speeds without a sample and hold leads to a number of error sources. The design of the converter is optimized to minimize the effects of these error sources. Experimental results are presented and compared with theory.

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OpenAlex reports 52 citations for this work. Citation counts describe recorded attention and do not establish research quality.

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Available abstract

A monolithic, 8-bit, 250 megasample per second analog-to-digital converter (ADC) fabricated in an oxide-isolated bipolar process is described. The use of a flash ADC architecture at high speeds without a sample and hold leads to a number of error sources. The design of the converter is optimized to minimize the effects of these error sources. Experimental results are presented and compared with theory.

Key concepts: Analog-to-digital converter, Flash ADC, Bit (key), Successive approximation ADC, Sample and hold, 4-bit, Flash (photography), Sample (material)

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