2012•IEICE Transactions on ElectronicsRequires access
A 120-GHz Transmitter and Receiver Chipset with 9-Gbps Data Rate Using 65-nm CMOS Technology
Ryuichi Fujimoto, Mizuki Motoyoshi, Kyoya Takano, Uroschanit Yodprasit, Minoru Fujishima
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Abstract
The design and measured results of a 120-GHz transmitter and receiver chipset are described in this paper. A simple on-off keying (OOK) modulation is adopted for low power consumption. The proposed transmitter and receiver are fabricated using 65-nm CMOS technology. The current consumption of the transmitter and receiver are 19.2mA and 48.2mA respectively. A 9-Gbps PRBS is successfully transferred from the transmitter to the receiver with the bit error rate less than 10-9.