Power-Aware Design of Electronic System Level using Interoperation of Hybrid and Distributed Simulations

Power consumption is a big challenge in chip design. Decisions taken in early design phases have large impact on the power consumption. Generally, simulation-based Design Space Exploration (DSE) is computationally costly for large problems due the size of design space. Simulate the possible scenarios in a distributed fashion can decrease the time to find efficient solutions. In this paper we describe an approach using HLA (High level Architecture) that allows to distribute and simulate different scenarios of Electronic System Level (ESL) models and/or Register Transfer Level (RTL) models for collecting and grouping power estimation data in a centralized manner. These models can be described in C++, SystemC, SystemVerilog or Verilog. As case study, we use a benchmark composed of a scalable set of MPSoCs described in C++/SystemC. We also use a small project in SystemVerilog/Verilog to validate the power estimation data collecting from models described in these languages through the approach. The experimental results show that the proposed method can distribute and simulate different scenarios of Electronic System Level (ESL) models as well as Register Transfer Level (RTL) models and provide a unified view of power estimation data.