Resistance against power analysis attacks on adiabatic dynamic and adiabatic differential logics for smart card

Numerous articles and patents on the masking of logic gates in CMOS logic styles have been reported, however, less information is available with regards to comparing the single-rail and dual-rail on masking input logic values. This paper investigates single-rail and dual-rail logic families that have been developed by the logic designers for secure logic implementations in cryptographic system. The novelty of this work is that we evaluate the dynamic logic and differential logic for one-phase 2-inputs logic in adiabatic mode in SPICE simulation. We analyze the power consumption of logic circuit along 16 possible transitions of 2-inputs logic during one cycle. The power traces show that adiabatic differential logic families are masking the input logic values, because they consume constant power during pre-charge and evaluation phases that enables the circuit to resist against power analysis attacks. Based on our results, we deduce that adiabatic differential logic families are promising candidates for further development to obtain a far more robust secure logic for countermeasure against power analysis attacks in smart card.