A low phase noise all-digital programmable DLL-based clock generator

This paper proposes a low phase noise all-digital programmable DLL-based clock generator. The proposed clock generator is fabricated in a 0.18 μm standard CMOS process with a 1.8 V supply voltage. The proposed digital programmable DLL-based clock generator is easy migration over different processes and low power dissipation. The measurement results show that the input and output frequency ranges can operate 100 MHz ~ 600 MHz and 100 MHz ~ 1.2 GHz, respectively. At 800 MHz, the phase noise is -112.36 dBc @ 1MHz offset frequency. The total power consumption of the clock generator is 23.87 mW, and the active die area of the clock generator is 0.14 mm2.