Design of a CMOS test chip for package models and I/O characteristics verification

Reliable packages for modern chips are crucial for satisfactory system performance. In order to ascertain package's performance, an equivalent electrical model is plugged into circuit simulations and the package's performance characteristics can be analyzed. However, one implicit assumption designers make is that these equivalent electrical models are accurate for performance characterization of packages. For modern high-speed designs, verification of the accuracy of these models is imperative and can only be carried out on real-silicon. In addition, signal integrity for inter-chip communication is crucial from a systems perspective. To study the signal integrity of data under different PVT (process variation, voltage, and temperature) conditions, appropriate test structures are needed. Data can be subjected to controlled variations through these structures and its integrity can be studied. And finally, testing package reliability at high temperatures is important since on-chip temperatures are increasing dramatically as processes continue to scale. The test chip presented in this design is intended to allow 1) circuit and package designers to evaluate and validate the accuracy of package models under a variety of environment conditions; 2) system designers to evaluate package/system level signal integrity issue before actual chips are available; and 3) system designers to evaluate on-chip temperatures and to study thermal integrity of packages. The test chip includes a variety of features to achieve these goals. The test chip is fabricated at TSMC in a 0.18 μm CMOS process. The measurement results and the die microphotograph will be sent later as soon as they are available. This paper presents the layout based simulation results.