Hardware implementation and evaluation of the Flexible router architecture for NoCs

The core of the Network on Chips is the router; therefore it is needed to design routers that meet the requirements of performance, area and power. In order to improve its performance, some techniques tend to increase the number of buffers, but it is responsible for a large portion of the router area and power. In the Flexible router architecture, the performance of the router increased in terms of increasing the saturation rate while having the same number of buffers as the Base router. Moreover, it was found that at high injection rates, the Flexible router outperforms the base router by near 14.3% in throughput, 27.6% of Latency and 15% increase in saturation point for uniform random traffic. This Paper focuses on hardware implementation and evaluation of the Flexible Router to verify its functionality and evaluate its performance compared to the base router. We use a cycle-accurate NoC simulation system implemented in Verilog HDL under uniform, neighbor, and hotspot traffic patterns.