A Partial Reconfiguration based Approach for Frequency Synthesis using FPGA

In order to obtain clocks needed for high speed, high-density designs, dedicated FPGA clock managers are becoming a necessity. The flexibility and programmability they provide is critical to the scope of applications they can support. Recent FPGA architectures, such as Xilinx Virtex Series, allow for partial and dynamic run-time reconfiguration. The FPGA fabric can modify its configuration data at run-time, enabling substitution of specific portions of an implemented hardware design causing the system to be adapted to the needs of the application. This Paper outlines a new approach of Digital Frequency Synthesis in conjunction with FPGA clock managers. The proposed implementation carries out the frequency synthesis using Dynamic Reconfiguration Port (DRP) of a DCM primitive through the Reconfigurable module in the Fabric. The design highlights Partial Reconfiguration based design approaches which dynamically reconfigures the clock frequency of a DCM according to the variable needs of the running application. Both the output frequency and phase can be precisely and rapidly manipulated on-the Fly. The suggested architecture is first simulated, implemented, and experimentally verified on a Virtex-5 FPGA board.