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Design on SOC module-level functional verification platform

He Zhang, Chunyu Wu, Wenjing Zhang, Jiwei Wang

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Abstract

In the traditional IP verification methodology, module level verification platform have limitations such as uncontrollability, low efficiency, huge workload, long verification time and poor reusability. To resolve these problems, a SOC function verification virtual platform based on bus transaction level strategy is proposed. The virtual verification platform is composed of system component function models, which are described by high level abstraction modeling methods. The platform provides incentives in bus transaction mode based on simulation. The experimental results of practical application show that the platform can improve IP verification efficiency and enhance IP verification reusability. The practical construction and methodology can be used in other function verification platform.

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What this paper is about

In the traditional IP verification methodology, module level verification platform have limitations such as uncontrollability, low efficiency, huge workload, long verification time and poor reusability. To resolve these problems, a SOC function verification virtual platform based on bus transaction level strategy is proposed. The virtual verification platform is composed of system component function models, which are described by high level abstraction modeling methods. The platform provides incentives in bus transaction mode based on simulation. The experimental results of practical application show that the platform can improve IP verification efficiency and enhance IP verification reusability. The practical construction and methodology can be used in other function verification platform.

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Available abstract

In the traditional IP verification methodology, module level verification platform have limitations such as uncontrollability, low efficiency, huge workload, long verification time and poor reusability. To resolve these problems, a SOC function verification virtual platform based on bus transaction level strategy is proposed. The virtual verification platform is composed of system component function models, which are described by high level abstraction modeling methods. The platform provides incentives in bus transaction mode based on simulation. The experimental results of practical application show that the platform can improve IP verification efficiency and enhance IP verification reusability. The practical construction and methodology can be used in other function verification platform.

Key concepts: Functional verification, Computer science, Reusability, Intelligent verification, Embedded system, High-level verification, Transaction-level modeling, Workload

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