NBTI-aware power gating for concurrent leakage and aging optimization

Power and reliability are known to be intrinsically conflicting metrics: traditional solutions to improve reliability such as redundancy, increase of voltage levels, and up-sizing of critical devices do contrast with traditional low-power solutions, which rely on small devices and scaled supply voltages. The emergence of Negative Bias Temperature Instability (NBTI) as the most relevant source of unreliability in sub-90nm technologies has even exacerbated this incompatibility of the two metrics: NBTI manifests itself as an increase of the propagation delay over time, which adds up to the delay penalty introduced by most low-power design solutions. In this work, we show how the most widely adopted leakage reduction solution, that is, power-gating, can overcome this conflict, and how it can be used to naturally reduce the effects of NBTI on delay. Based on this important property, we present a methodology for NBTI-aware power gating that allows synthesizing low-leakage circuits with maximum lifetime.