2010•AIP conference proceedingsRequires access
Novel Adiabatic-CMOS Interfaces
Neha Arora, Bharat Singh, Tripti Sharma, Kulbhushan Sharma, Ravi B. Patel, Bharat Singh
Open publisher page 2 citations
Abstract
This paper describes the design of low power adiabatic‐CMOS/CMOS‐adiabatic logic interface circuits. The circuit provides interfacing between several recently proposed low‐power adiabatic logic circuits and traditional digital CMOS circuits. One advantage of this design is that the energy loss per cycle for these interfaces is negligibly small. All the simulation has been done with BSIM 3v3 90 nm CMOS technology.