Gate Current Modeling and Optimization of High-k Gate Stack MOSFET Structure in Nano Scale Regime

In this paper, an analytical model has been developed for gate tunneling current in nano scale MOSFET with high-k dielectric stack as gate insulator. A computationally efficient model for gate tunneling current through different high-k gate stack structure is presented. The proposed model has been successfully used for different gate stack dielectric simply by adjusting two fitting parameters. The model predictions are compared with the two-dimensional Santaurus device simulation. Good agreement between the model predictions and device simulation results has been obtained. The effects of interfacial oxide thickness, type of gate stack and reverse gate stack on the gate tunneling current have also been studied as a function of gate voltages for a given equivalent oxide thickness (EOT) of 1.0 nm. It was also shown that smaller inter oxide layer thickness reduces gate leakages current with the introduction of high-k gate stack structure in place of individual high-k dielectric or SiO2.