The discrete event simulation computer - DESC

Simulation of large models on digital computers is often limited by the high computational expenses. The Discrete Event Simulation Computer (DESC) reported here improves simulation performance through an exploitation of parallelism inherent in simulation, with regard to list processing, random number generation, statistical analysis and program control. The DESC consists of a set of nodes that communicate via FIFO-buffered channels (i.e. do not share memory among nodes). In order to achieve high system throughput dedicated hardware modules were developed; this includes new concepts for a list processor and a hardware random number generator for uniform deviates.The implementation of simulation languages such as SIMULA, SIMSCRIPT or GPSS is conceptually straightforward. We chose SIMULA as the frame language concept. Metrics applicable to simulation throughput and simulation costs are defined and compared with the CD CYBER 175.