ScholarLens Back to search
1974•IEEE Transactions on CommunicationsRequires access

Response of an All Digital Phase-Locked Loop

J. Garodnick, J.D. Greco, Donald L. Schilling

Open publisher page 45 citations

Abstract

An all digital phase-locked loop (DPLL) is designed, analyzed, and tested. Three specific configurations are considered, generating first, second, and third order DPLL's; and it is found, using a computer simulation of a noise spike, and verified experimentally, that of these configurations the second-order system is optimum from the standpoint of threshold extension. This substantiates results obtained for analog PLL's.

About this research paper

What this paper is about

An all digital phase-locked loop (DPLL) is designed, analyzed, and tested. Three specific configurations are considered, generating first, second, and third order DPLL's; and it is found, using a computer simulation of a noise spike, and verified experimentally, that of these configurations the second-order system is optimum from the standpoint of threshold extension. This substantiates results obtained for analog PLL's.

Why it matters

OpenAlex reports 45 citations for this work. Citation counts describe recorded attention and do not establish research quality.

Key contribution

A contribution statement is not available in the OpenAlex record.

Method / approach

Method details are not available in the OpenAlex metadata.

Main findings

Findings are not separately available in the OpenAlex metadata.

Limitations

Limitations are not available in the OpenAlex metadata.

Applications

Application details are not available in the OpenAlex metadata.

Available abstract

An all digital phase-locked loop (DPLL) is designed, analyzed, and tested. Three specific configurations are considered, generating first, second, and third order DPLL's; and it is found, using a computer simulation of a noise spike, and verified experimentally, that of these configurations the second-order system is optimum from the standpoint of threshold extension. This substantiates results obtained for analog PLL's.

Key concepts: DPLL algorithm, Phase-locked loop, Loop (graph theory), PLL multibit, Noise (video), Phase (matter), Control theory (sociology), Third order

Related papers

Related paper 1Related paper 2Related paper 3
Back to paper searchBrowse research topicsOriginal source
Response of an All Digital Phase-Locked Loop — Research Paper | ScholarLens