Static timing analysis in Dual-Rail Precharge logic based DPA resistant circuit design

Dual-Rail Precharge (DRP) logic is an efficient countermeasure against Differential Power Analysis (DPA) attack. The existing DRP logic based design method starts from a standard design flow supported by commercial EDA tools. Virtual single ended gates, instead of real DRP logic gates, are used during synthesis, placement and routing. As a result, static timing analysis becomes a problem at these design phases. In this paper, we discuss the transition behavior of DRP logic, and present a method to build the delay models of virtual single ended gates. By using these delay models, the static timing analysis for the virtual single ended circuit can represents the actual signal propagating delay in DRP logic circuit. Hence the EDA tools can do timing optimization with accurate delay information. Experimental results on a DRP logic based AES cryptographic coprocessor show the effectiveness of the proposed method.